During the trip, Dr. Chandan Kumar Jha is going to attend the 33rd IEEE Asian Test Symposium as well as the 38th International Conference on VLSI Design (Very Large-Scale Integration Design). At the conferences, he will present new findings in the field of in-memory computing, approximate circuits, and large language models (LLMs) for verification. In addition, he will deliver a tutorial on employing LLMs for Hardware Verification in VLSI Design.

By sharing recent findings with research groups at the leading Indian research institutes, IIT Gandhinagar, IIT Bombay, and IIIT Bangalore, the trip aims to facilitate knowledge exchange at the intersection of in-memory computing and approximate circuits. The talks and follow-up discussions will also provide opportunities to network, discuss future collaborations, and exchange ideas with researchers from both academia and industry. By identifying complementary areas of research, the trip also serves to seed long-term international partnerships and lay the basis for potential joint projects and publications.

Funding recipient:

Dr. Chandan Kumar Jha (Faculty 3 – Mathematics & Computer Science)

Funding period:

14.12.2024-09.01.2025

Are you interested in the DSC Seed Grant?

You can find more information about the DSC Seed Grant here.

For questions, please contact:

Dr. Lena Steinmann
DSC Coordinator
Tel. +49 (421) 218 - 63941
E-Mail: lena.steinmannprotect me ?!uni-bremenprotect me ?!.de